DesignWare PHY IP for PCIe 5.0 in Silicon Operating at 32 GT/s HD

This video shows the Synopsys PHY IP for PCI Express (PCIe) 5.0 operating at 32 GT/s data rate across a long compliance channel. The wide open receiver eye and the bath tub plots show the PHY meeting the PCIe 5.0 specification for performance and bit error rate. Accelerate your shift to PCIe 5.0 designs with the Synopsys DesignWare Controller and PHY IP solutions. https://www.synopsys.com/pcie.